1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming a self-passivated copper damascene structure.
2) Description of the Prior Art
In integrated circuit technology, increased performance (i.e. faster processing) and greater packaging density are continually demanded. A promising approach to increasing performance is the use of copper damascene wiring. By reducing RC delay, copper damascene wiring provides improved performance.
However, as packaging densities of integrated circuits continue to increase, interconnect structures must shrink. To shrink interconnect structures improved step coverage is required. For damascene wiring metal must fill not only trenches, but vias as well. To realize copper damascene wiring, new technologies with excellent step coverage, such as MOCVD and electroplating have been developed. A dielectric barrier layer, such as nitride, has to be put on top of the damascene structure to prevent copper diffusion out of the damascene structure. A nitride barrier layer, because of its high dielectric constant (K-value) will result in high intra-layer capacitance, increasing RC delay.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,913,147(Dubin et al.) shows a layer over a Cu alloy plug.
U.S. Pat. No. 5,728,629(Mizuno et al.) shows a passivation process.
U.S. Pat. No. 5,714,418(Bia et al.) discloses a Cu interconnect.
U.S. Pat. No. 5,391,517(Gelatos et al.) discloses a Cu interconnect.
U.S. Pat. No. 6,046,108(Liu et al.) shows a layer over a Cu plug.